op_names.c
1 /*
2  * $Id: op_names.c,v 1.5 2003/12/01 09:10:15 troth Exp $
3  *
4  ****************************************************************************
5  *
6  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
7  * Copyright (C) 2001, 2002, 2003 Theodore A. Roth
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22  *
23  ****************************************************************************
24  */
25 
26 #include "op_names.h"
27 
28 /*
29  * Define a global array of opcode Name strings.
30  */
31 
32 /* *INDENT-OFF */
33 char *global_opcode_name[NUM_OPCODE_HANLDERS] = {
34  /* opcodes with no operands */
35  "BREAK", /* 0x9598 - 1001 0101 1001 1000 | BREAK */
36  "EICALL", /* 0x9519 - 1001 0101 0001 1001 | EICALL */
37  "EIJMP", /* 0x9419 - 1001 0100 0001 1001 | EIJMP */
38  "ELPM", /* 0x95D8 - 1001 0101 1101 1000 | ELPM */
39  "ESPM", /* 0x95F8 - 1001 0101 1111 1000 | ESPM */
40  "ICALL", /* 0x9509 - 1001 0101 0000 1001 | ICALL */
41  "IJMP", /* 0x9409 - 1001 0100 0000 1001 | IJMP */
42  "LPM", /* 0x95C8 - 1001 0101 1100 1000 | LPM */
43  "NOP", /* 0x0000 - 0000 0000 0000 0000 | NOP */
44  "RET", /* 0x9508 - 1001 0101 0000 1000 | RET */
45  "RETI", /* 0x9518 - 1001 0101 0001 1000 | RETI */
46  "SLEEP", /* 0x9588 - 1001 0101 1000 1000 | SLEEP */
47  "SPM", /* 0x95E8 - 1001 0101 1110 1000 | SPM */
48  "WDR", /* 0x95A8 - 1001 0101 1010 1000 | WDR */
49 
50  /* opcode with a single register (Rd) as operand */
51  "ASR", /* 0x9405 - 1001 010d dddd 0101 | ASR */
52  "COM", /* 0x9400 - 1001 010d dddd 0000 | COM */
53  "DEC", /* 0x940A - 1001 010d dddd 1010 | DEC */
54  "ELPM_Z", /* 0x9006 - 1001 000d dddd 0110 | ELPM */
55  "ELPM_Z_incr", /* 0x9007 - 1001 000d dddd 0111 | ELPM */
56  "INC", /* 0x9403 - 1001 010d dddd 0011 | INC */
57  "LDS", /* 0x9000 - 1001 000d dddd 0000 | LDS */
58  "LD_X", /* 0x900C - 1001 000d dddd 1100 | LD */
59  "LD_X_decr", /* 0x900E - 1001 000d dddd 1110 | LD */
60  "LD_X_incr", /* 0x900D - 1001 000d dddd 1101 | LD */
61  "LD_Y_decr", /* 0x900A - 1001 000d dddd 1010 | LD */
62  "LD_Y_incr", /* 0x9009 - 1001 000d dddd 1001 | LD */
63  "LD_Z_decr", /* 0x9002 - 1001 000d dddd 0010 | LD */
64  "LD_Z_incr", /* 0x9001 - 1001 000d dddd 0001 | LD */
65  "LPM_Z", /* 0x9004 - 1001 000d dddd 0100 | LPM */
66  "LPM_Z_incr", /* 0x9005 - 1001 000d dddd 0101 | LPM */
67  "LSR", /* 0x9406 - 1001 010d dddd 0110 | LSR */
68  "NEG", /* 0x9401 - 1001 010d dddd 0001 | NEG */
69  "POP", /* 0x900F - 1001 000d dddd 1111 | POP */
70  "PUSH", /* 0x920F - 1001 001d dddd 1111 | PUSH */
71  "ROR", /* 0x9407 - 1001 010d dddd 0111 | ROR */
72  "STS", /* 0x9200 - 1001 001d dddd 0000 | STS */
73  "ST_X", /* 0x920C - 1001 001d dddd 1100 | ST */
74  "ST_X_decr", /* 0x920E - 1001 001d dddd 1110 | ST */
75  "ST_X_incr", /* 0x920D - 1001 001d dddd 1101 | ST */
76  "ST_Y_decr", /* 0x920A - 1001 001d dddd 1010 | ST */
77  "ST_Y_incr", /* 0x9209 - 1001 001d dddd 1001 | ST */
78  "ST_Z_decr", /* 0x9202 - 1001 001d dddd 0010 | ST */
79  "ST_Z_incr", /* 0x9201 - 1001 001d dddd 0001 | ST */
80  "SWAP", /* 0x9402 - 1001 010d dddd 0010 | SWAP */
81 
82  /* opcodes with two 5-bit register (Rd and Rr) operands */
83  "ADC", /* 0x1C00 - 0001 11rd dddd rrrr | ADC or ROL */
84  "ADD", /* 0x0C00 - 0000 11rd dddd rrrr | ADD or LSL */
85  "AND", /* 0x2000 - 0010 00rd dddd rrrr | AND or TST
86  or LSL */
87  "CP", /* 0x1400 - 0001 01rd dddd rrrr | CP */
88  "CPC", /* 0x0400 - 0000 01rd dddd rrrr | CPC */
89  "CPSE", /* 0x1000 - 0001 00rd dddd rrrr | CPSE */
90  "EOR", /* 0x2400 - 0010 01rd dddd rrrr | EOR or CLR */
91  "MOV", /* 0x2C00 - 0010 11rd dddd rrrr | MOV */
92  "MUL", /* 0x9C00 - 1001 11rd dddd rrrr | MUL */
93  "OR", /* 0x2800 - 0010 10rd dddd rrrr | OR */
94  "SBC", /* 0x0800 - 0000 10rd dddd rrrr | SBC */
95  "SUB", /* 0x1800 - 0001 10rd dddd rrrr | SUB */
96 
97  /* opcodes with two 4-bit register (Rd and Rr) operands */
98  "MOVW", /* 0x0100 - 0000 0001 dddd rrrr | MOVW */
99  "MULS", /* 0x0200 - 0000 0010 dddd rrrr | MULS */
100  "MULSU", /* 0x0300 - 0000 0011 dddd rrrr | MULSU */
101 
102  /* opcodes with two 3-bit register (Rd and Rr) operands */
103  "FMUL", /* 0x0308 - 0000 0011 0ddd 1rrr | FMUL */
104  "FMULS", /* 0x0380 - 0000 0011 1ddd 0rrr | FMULS */
105  "FMULSU", /* 0x0388 - 0000 0011 1ddd 1rrr | FMULSU */
106 
107  /* opcodes with a register (Rd) and a constant data (K) as operands */
108  "ANDI", /* 0x7000 - 0111 KKKK dddd KKKK | CBR or
109  ANDI */
110  "CPI", /* 0x3000 - 0011 KKKK dddd KKKK | CPI */
111  "LDI", /* 0xE000 - 1110 KKKK dddd KKKK | LDI */
112  "ORI", /* 0x6000 - 0110 KKKK dddd KKKK | SBR or ORI */
113  "SBCI", /* 0x4000 - 0100 KKKK dddd KKKK | SBCI */
114  "SUBI", /* 0x5000 - 0101 KKKK dddd KKKK | SUBI */
115 
116  /* opcodes with a register (Rd) and a register bit number (b) as
117  operands */
118  "BLD", /* 0xF800 - 1111 100d dddd 0bbb | BLD */
119  "BST", /* 0xFA00 - 1111 101d dddd 0bbb | BST */
120  "SBRC", /* 0xFC00 - 1111 110d dddd 0bbb | SBRC */
121  "SBRS", /* 0xFE00 - 1111 111d dddd 0bbb | SBRS */
122 
123  /* opcodes with a relative 7-bit address (k) and a register bit number (b)
124  as operands */
125  "BRBC", /* 0xF400 - 1111 01kk kkkk kbbb | BRBC */
126  "BRBS", /* 0xF000 - 1111 00kk kkkk kbbb | BRBS */
127 
128  /* opcodes with a 6-bit address displacement (q) and a register (Rd) as
129  operands */
130  "LDD_Y", /* 0x8008 - 10q0 qq0d dddd 1qqq | LDD */
131  "LDD_Z", /* 0x8000 - 10q0 qq0d dddd 0qqq | LDD */
132  "STD_Y", /* 0x8208 - 10q0 qq1d dddd 1qqq | STD */
133  "STD_Z", /* 0x8200 - 10q0 qq1d dddd 0qqq | STD */
134 
135  /* opcodes with a absolute 22-bit address (k) operand */
136  "CALL", /* 0x940E - 1001 010k kkkk 111k | CALL */
137  "JMP", /* 0x940C - 1001 010k kkkk 110k | JMP */
138 
139  /* opcode with a sreg bit select (s) operand */
140  "BCLR", /* 0x9488 - 1001 0100 1sss 1000 | BCLR or
141  CL{C,Z,N,V,S,H,T,I} */
142  "BSET", /* 0x9408 - 1001 0100 0sss 1000 | BSET or
143  SE{C,Z,N,V,S,H,T,I} */
144 
145  /* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
146  "ADIW", /* 0x9600 - 1001 0110 KKdd KKKK | ADIW */
147  "SBIW", /* 0x9700 - 1001 0111 KKdd KKKK | SBIW */
148 
149  /* opcodes with a 5-bit IO Addr (A) and register bit number (b) as
150  operands */
151  "CBI", /* 0x9800 - 1001 1000 AAAA Abbb | CBI */
152  "SBI", /* 0x9A00 - 1001 1010 AAAA Abbb | SBI */
153  "SBIC", /* 0x9900 - 1001 1001 AAAA Abbb | SBIC */
154  "SBIS", /* 0x9B00 - 1001 1011 AAAA Abbb | SBIS */
155 
156  /* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
157  "IN", /* 0xB000 - 1011 0AAd dddd AAAA | IN */
158  "OUT", /* 0xB800 - 1011 1AAd dddd AAAA | OUT */
159 
160  /* opcodes with a relative 12-bit address (k) operand */
161  "RCALL", /* 0xD000 - 1101 kkkk kkkk kkkk | RCALL */
162  "RJMP" /* 0xC000 - 1100 kkkk kkkk kkkk | RJMP */
163 };
164 
165 /* *INDENT-ON */

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