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op_names.c
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/*
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* $Id: op_names.c,v 1.5 2003/12/01 09:10:15 troth Exp $
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*
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****************************************************************************
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*
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* simulavr - A simulator for the Atmel AVR family of microcontrollers.
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* Copyright (C) 2001, 2002, 2003 Theodore A. Roth
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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****************************************************************************
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*/
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#include "op_names.h"
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/*
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* Define a global array of opcode Name strings.
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*/
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/* *INDENT-OFF */
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char
*global_opcode_name[NUM_OPCODE_HANLDERS] = {
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/* opcodes with no operands */
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"BREAK"
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/* 0x9598 - 1001 0101 1001 1000 | BREAK */
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"EICALL"
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/* 0x9519 - 1001 0101 0001 1001 | EICALL */
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"EIJMP"
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/* 0x9419 - 1001 0100 0001 1001 | EIJMP */
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"ELPM"
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/* 0x95D8 - 1001 0101 1101 1000 | ELPM */
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"ESPM"
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/* 0x95F8 - 1001 0101 1111 1000 | ESPM */
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"ICALL"
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/* 0x9509 - 1001 0101 0000 1001 | ICALL */
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"IJMP"
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/* 0x9409 - 1001 0100 0000 1001 | IJMP */
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"LPM"
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/* 0x95C8 - 1001 0101 1100 1000 | LPM */
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"NOP"
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/* 0x0000 - 0000 0000 0000 0000 | NOP */
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"RET"
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/* 0x9508 - 1001 0101 0000 1000 | RET */
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"RETI"
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/* 0x9518 - 1001 0101 0001 1000 | RETI */
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"SLEEP"
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/* 0x9588 - 1001 0101 1000 1000 | SLEEP */
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"SPM"
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/* 0x95E8 - 1001 0101 1110 1000 | SPM */
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"WDR"
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/* 0x95A8 - 1001 0101 1010 1000 | WDR */
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/* opcode with a single register (Rd) as operand */
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"ASR"
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/* 0x9405 - 1001 010d dddd 0101 | ASR */
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"COM"
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/* 0x9400 - 1001 010d dddd 0000 | COM */
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"DEC"
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/* 0x940A - 1001 010d dddd 1010 | DEC */
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"ELPM_Z"
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/* 0x9006 - 1001 000d dddd 0110 | ELPM */
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"ELPM_Z_incr"
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/* 0x9007 - 1001 000d dddd 0111 | ELPM */
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"INC"
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/* 0x9403 - 1001 010d dddd 0011 | INC */
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"LDS"
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/* 0x9000 - 1001 000d dddd 0000 | LDS */
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"LD_X"
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/* 0x900C - 1001 000d dddd 1100 | LD */
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"LD_X_decr"
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/* 0x900E - 1001 000d dddd 1110 | LD */
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"LD_X_incr"
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/* 0x900D - 1001 000d dddd 1101 | LD */
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"LD_Y_decr"
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/* 0x900A - 1001 000d dddd 1010 | LD */
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"LD_Y_incr"
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/* 0x9009 - 1001 000d dddd 1001 | LD */
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"LD_Z_decr"
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/* 0x9002 - 1001 000d dddd 0010 | LD */
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"LD_Z_incr"
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/* 0x9001 - 1001 000d dddd 0001 | LD */
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"LPM_Z"
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/* 0x9004 - 1001 000d dddd 0100 | LPM */
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"LPM_Z_incr"
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/* 0x9005 - 1001 000d dddd 0101 | LPM */
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"LSR"
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/* 0x9406 - 1001 010d dddd 0110 | LSR */
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"NEG"
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/* 0x9401 - 1001 010d dddd 0001 | NEG */
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"POP"
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/* 0x900F - 1001 000d dddd 1111 | POP */
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"PUSH"
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/* 0x920F - 1001 001d dddd 1111 | PUSH */
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"ROR"
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/* 0x9407 - 1001 010d dddd 0111 | ROR */
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"STS"
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/* 0x9200 - 1001 001d dddd 0000 | STS */
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"ST_X"
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/* 0x920C - 1001 001d dddd 1100 | ST */
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"ST_X_decr"
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/* 0x920E - 1001 001d dddd 1110 | ST */
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"ST_X_incr"
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/* 0x920D - 1001 001d dddd 1101 | ST */
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"ST_Y_decr"
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/* 0x920A - 1001 001d dddd 1010 | ST */
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"ST_Y_incr"
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/* 0x9209 - 1001 001d dddd 1001 | ST */
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"ST_Z_decr"
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/* 0x9202 - 1001 001d dddd 0010 | ST */
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"ST_Z_incr"
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/* 0x9201 - 1001 001d dddd 0001 | ST */
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"SWAP"
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/* 0x9402 - 1001 010d dddd 0010 | SWAP */
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/* opcodes with two 5-bit register (Rd and Rr) operands */
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"ADC"
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/* 0x1C00 - 0001 11rd dddd rrrr | ADC or ROL */
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"ADD"
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/* 0x0C00 - 0000 11rd dddd rrrr | ADD or LSL */
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"AND"
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/* 0x2000 - 0010 00rd dddd rrrr | AND or TST
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or LSL */
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"CP"
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/* 0x1400 - 0001 01rd dddd rrrr | CP */
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"CPC"
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/* 0x0400 - 0000 01rd dddd rrrr | CPC */
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"CPSE"
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/* 0x1000 - 0001 00rd dddd rrrr | CPSE */
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"EOR"
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/* 0x2400 - 0010 01rd dddd rrrr | EOR or CLR */
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"MOV"
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/* 0x2C00 - 0010 11rd dddd rrrr | MOV */
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"MUL"
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/* 0x9C00 - 1001 11rd dddd rrrr | MUL */
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"OR"
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/* 0x2800 - 0010 10rd dddd rrrr | OR */
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"SBC"
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/* 0x0800 - 0000 10rd dddd rrrr | SBC */
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"SUB"
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/* 0x1800 - 0001 10rd dddd rrrr | SUB */
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/* opcodes with two 4-bit register (Rd and Rr) operands */
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"MOVW"
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/* 0x0100 - 0000 0001 dddd rrrr | MOVW */
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"MULS"
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/* 0x0200 - 0000 0010 dddd rrrr | MULS */
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"MULSU"
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/* 0x0300 - 0000 0011 dddd rrrr | MULSU */
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/* opcodes with two 3-bit register (Rd and Rr) operands */
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"FMUL"
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/* 0x0308 - 0000 0011 0ddd 1rrr | FMUL */
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"FMULS"
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/* 0x0380 - 0000 0011 1ddd 0rrr | FMULS */
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"FMULSU"
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/* 0x0388 - 0000 0011 1ddd 1rrr | FMULSU */
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/* opcodes with a register (Rd) and a constant data (K) as operands */
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"ANDI"
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/* 0x7000 - 0111 KKKK dddd KKKK | CBR or
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ANDI */
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"CPI"
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/* 0x3000 - 0011 KKKK dddd KKKK | CPI */
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"LDI"
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/* 0xE000 - 1110 KKKK dddd KKKK | LDI */
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"ORI"
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/* 0x6000 - 0110 KKKK dddd KKKK | SBR or ORI */
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"SBCI"
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/* 0x4000 - 0100 KKKK dddd KKKK | SBCI */
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"SUBI"
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/* 0x5000 - 0101 KKKK dddd KKKK | SUBI */
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/* opcodes with a register (Rd) and a register bit number (b) as
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operands */
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"BLD"
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/* 0xF800 - 1111 100d dddd 0bbb | BLD */
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"BST"
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/* 0xFA00 - 1111 101d dddd 0bbb | BST */
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"SBRC"
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/* 0xFC00 - 1111 110d dddd 0bbb | SBRC */
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"SBRS"
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/* 0xFE00 - 1111 111d dddd 0bbb | SBRS */
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/* opcodes with a relative 7-bit address (k) and a register bit number (b)
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as operands */
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"BRBC"
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/* 0xF400 - 1111 01kk kkkk kbbb | BRBC */
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"BRBS"
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/* 0xF000 - 1111 00kk kkkk kbbb | BRBS */
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/* opcodes with a 6-bit address displacement (q) and a register (Rd) as
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operands */
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"LDD_Y"
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/* 0x8008 - 10q0 qq0d dddd 1qqq | LDD */
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"LDD_Z"
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/* 0x8000 - 10q0 qq0d dddd 0qqq | LDD */
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"STD_Y"
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/* 0x8208 - 10q0 qq1d dddd 1qqq | STD */
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"STD_Z"
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/* 0x8200 - 10q0 qq1d dddd 0qqq | STD */
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/* opcodes with a absolute 22-bit address (k) operand */
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"CALL"
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/* 0x940E - 1001 010k kkkk 111k | CALL */
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"JMP"
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/* 0x940C - 1001 010k kkkk 110k | JMP */
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/* opcode with a sreg bit select (s) operand */
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"BCLR"
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/* 0x9488 - 1001 0100 1sss 1000 | BCLR or
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CL{C,Z,N,V,S,H,T,I} */
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"BSET"
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/* 0x9408 - 1001 0100 0sss 1000 | BSET or
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SE{C,Z,N,V,S,H,T,I} */
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/* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
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"ADIW"
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/* 0x9600 - 1001 0110 KKdd KKKK | ADIW */
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"SBIW"
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/* 0x9700 - 1001 0111 KKdd KKKK | SBIW */
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/* opcodes with a 5-bit IO Addr (A) and register bit number (b) as
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operands */
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"CBI"
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/* 0x9800 - 1001 1000 AAAA Abbb | CBI */
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"SBI"
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/* 0x9A00 - 1001 1010 AAAA Abbb | SBI */
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"SBIC"
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/* 0x9900 - 1001 1001 AAAA Abbb | SBIC */
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"SBIS"
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/* 0x9B00 - 1001 1011 AAAA Abbb | SBIS */
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/* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
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"IN"
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/* 0xB000 - 1011 0AAd dddd AAAA | IN */
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"OUT"
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/* 0xB800 - 1011 1AAd dddd AAAA | OUT */
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/* opcodes with a relative 12-bit address (k) operand */
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"RCALL"
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/* 0xD000 - 1101 kkkk kkkk kkkk | RCALL */
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"RJMP"
/* 0xC000 - 1100 kkkk kkkk kkkk | RJMP */
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};
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/* *INDENT-ON */
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