The lang/freehdl port
freehdl-0.0.7p5 – open-source (C++ generating) VHDL simulator
Description
FreeHDL is a compiler/simulator suite for the hardware description
language VHDL. VHDL'93 as well as VHDL'87 standards are supported.
FreeHDL translates the original VHDL source FILEs into C++. Then, the
C++ source can be compiled and linked to the kernel to build the
simulation program. Starting the generated executable will simulate the
corresponding VHDL model. The actual build process to generate the
simulator from the VHDL source is a complex process which is handled by
the gvhdl script.
WWW: http://www.freehdl.seul.org/
- Only for arches
-
aarch64
aarch64
alpha
alpha
amd64
amd64
arm
arm
hppa
hppa
i386
i386
mips64
mips64
mips64el
mips64el
powerpc
powerpc
sh
sparc64
sparc64
- Categories:
-
cad
lang
Library dependencies
Build dependencies
Run dependencies